In the commonly used integrated circuits with very large scale integration (VLSI) for data processing systems, which circuits perform a plurality of functions, with high parallelism of the information transferred through input/output terminals, there is the problem of harmonizing wide versatility of operation with the number of input/output terminals or pins of the circuit, for transferring data and control signals, which has to be as limited as possible.
This is necessary for two reasons:
1) Each input/output terminal requires, on the integrated circuit, a connection pad which takes away considerable space from the active part of the chip. PA1 2) Each input/output terminal, in particular if it is to perform control functions, requires internal and external drive logic which increases the complexity of the system, inside and outside the integrated circuit, and its cost.
On the other hand, an integrated circuit has to be as flexible as possible, so as to be able to work, within the same system architecture with different system configurations, whether hardware, software or firmware, if not also for reasons of compatibility of use in different architectures.
This implies, for example, that it must be able to work with several different processors, be able to be inserted into a system under differing modularities, function with different SWs and FWs, and guarantee SW and FW compatibility with other integrated circuits from the same family which exist on the market.
As a specific example, an integrated circuit intended to be connected to a system bus, in particular a bridge unit for interconnection between a system bus and one or more local buses, must be able to recognize itself as being a unit addressed and selected through the system bus.
For this purpose the unit is provided with internal logic which defines a range of addresses, using a base and an upper limit of the range, through which the unit identifies itself as being a selected unit.
In other words, in modern integrated circuits the selection logic of the chip is not external and the chip is not selected by a chip select signal received externally, but internally.
Obviously the selection logic cannot be rigid and predetermined since otherwise several integrated circuits of the same type, connected to the same system bus, would all recognize themselves as being selected devices, contradicting the selection concept.
The selection logic should therefore be programmable.
The programming cannot be fixed, carried out at production level, since this would exclude any possibility of system reconfiguration, but variable depending on the system requirements and able to be carried out automatically by the system each time it is turned on, without the need for external interventions.
However, with this approach the problem is not solved, but merely shifted upstream.
Thus, when the system is turned on, the integrated circuit must be able to configure itself on the basis of information from outside, and hence must first of all identify itself as the destination of the information coming from the outside.
This problem can be solved in two ways.
The first solution is to provide a number of input terminals for control signals which make it possible to interpret the information received on other terminals, as programming information.
Obviously this solution is partial since it is not in harmony with the requirement to minimize the number of terminals.
In many cases it is even impracticable, since it is not possible to provide additional control terminals to perform this function.
The second solution is to provide a dual configuration/logic function for a number of input logic terminals based on the state of another system signal, for example an initializing RESET signal.
In other words, when the system is turned on and the system RESET signal is enabled, a few input terminals of the integrated circuit can perform the role of selection terminals, whilst others can be used to receive information which is used as configuration information.
This solution requires the use, outside the integrated circuit, of logic, necessarily active in the reset phase, for making the logic terminals perform the dual configuration/logic function and greater complexity of the internal logic of the integrated circuit, the lengthening of the logic chain downstream of the input terminals and consequent impairment of the timings and performance of the circuit.
With this solution it is possible to configure the integrated circuit, in the system reset phase, with a programmable "default" configuration, which at the least allows activation of the system.
It is also possible, in the operational phase, to refine and reconfigure the integrated circuit dynamically so as to make it operate in the desired mode, by sending SW or FW instructions which are recognized by the integrated circuit.
However, the greater the information required for configuring the integrated circuit in the reset phase (for example even to define just one window of addresses as the selection range may require as many as 32 bits), the more complex is the external and internal initialization logic.